Continuing advances in the semiconductor industry have made possible the production of integrated circuits with increasingly larger numbers of logic or other elements on a single chip. The increasing complexity of LSI or VLSI chips made possible by these advances and the high costs involved in initial production of a chip from a logic design have made logic simulation an important step in the chip design process. Logic simulation techniques are available in the art for simulating operation of a logic design for a chip prior to the start of fabrication of the chip, to uncover any operational errors therein, and to permit redesign as necessary before committing the design to chip fabrication. Various logic simulation computer programs are known in the art for performing this function. In adition, hardware logic simulator networks in accordance with U.S. Pat. No. 4,527,249, now assigned to the assignee of this application, provide highly efficient techniques for simulating and testing logic device designs.
A different but somewhat related problem existing in the semiconductor industry is in the testing of manufactured chips. Even assuming a good, error-free logic design, it is well known that various faults and errors can enter into the production process which can result in functional defects in a manufactured chip. These faults can enter through a variety of causes in the numerous manufacturing process steps, and can affect any of the different gates, switches or lines on the chip. Although the causes of such errors are diverse, as a practical matter for testing purposes, they can be considered to occur on essentially a random basis anywhere in a chip.
This presents a problem for production testing, since for complex chips such as microprocessors or other VLSI circuits there are so many circuit elements and combinations of inputs and outputs that it becomes totally impractical to test all possible input combinations against the known design standard. With such complex chips it might take half an hour or even longer to run through all input combination sets, and of course a chip production rate of two per hour is not financially feasible on a commercial basis. Consequently, it has become standard practice to use a reduced or limited set of input states, or input vectors, carefully chosen with the intent of catching a predetermined percentage of all possible faults, for example 95%, which is common in commercial practice, or perhaps 98%, which is specified in some military applications. This typically gives the possibility of testing with perhaps only 100,000 or 500,000 input sets instead of many millions, and the reduced number of sets can be run through in a matter of seconds. If the input set is well chosen, this provides a workable and commercially acceptable production testing capability. However, the key questions remaining are how to select a reasonably compact set of inputs to test for a given percentage of all possible faults, and how to prove that a particular input test set will in fact test for the required percentage of faults.
One current technique for developing a test set of inputs is through a technique known as serial fault simulation. In this technique a logic simulation is first run on a correct network to determine the correct output "signature", then is run repeatedly with a given specific error being introduced on each pass. For example, a particular input for a particular gate is "stuck" to a logical one or logical zero, then some input sets and corresponding outputs are run on the design and checked to see whether that particular fault shows up as a change in the output signature for a given set of inputs. The process is then repeated for another "stuck" gate, and so on, until a set of data is built up that will detect a predetermined percentage of all such faults. The set can be compacted by eliminating redundancies, since a given input set may detect a number of different fault conditions. This serial technique, and several variants which are in use, take many runs through the logic design by the logic simulator, and are therefore very time-consuming.